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TaN and \hbox {Al}_{2}\hbox {O}_{3} Sidewall Gate-Etch Damage Influence on Program, Erase, and Retention of Sub-50-nm TANOS nand Flash Memory Cells

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4 Author(s)
Beug, M.F. ; Phys.-Tech. Bundesanstalt (PTB), Braunschweig, Germany ; Melde, T. ; Paul, J. ; Knoefler, R.

The sidewall gate-etch damage influence on the electrical behavior of 48-nm TaN/AI2O3/SiN/SiO2/Si (TANOS) NAND charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-k AI2O3 blocking-oxide layers and adversely affects the electrical performance and the mechanical stability of small-ground-rule TANOS cells. Both issues could be solved for 48-nm TANOS cells by the introduction of a new integration scheme, which includes a removable encapsulation liner. This SiN liner protects the TaN sidewall from the etch damage during the aggressive AI2O3 high-k etch process. The optimum of the 48-nm electrical cell performance was found for a 4-nm encapsulation liner thickness. In contrast to 48-nm TANOS cells, the encapsulation liner thickness does not affect the electrical performance of large 5-μm-long-and-wide memory cells. The memory cell performance dependence on the TANOS liner thickness and memory cell size is explained by a damaged AI2O3 region approximately 3-4 nm thick at the block oxide side wall. As a result, the reported etch damage exhibits a new scaling issue for TANOS memory cells around the 20-nm technology node when the total encapsulation liner thickness approaches half of the memory cell length.

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Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 6 )