By Topic

Low-Stress CMOS-Compatible Silicon Carbide Surface-Micromachining Technology—Part I: Process Development and Characterization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Frederic Nabki ; Université du Québec à Montréal, Montreal, Canada ; Tomas A. Dusatko ; Srikar Vengallatore ; Mourad N. El-Gamal

A low-temperature (<; 300 °C) low-stress microelectromechanical systems fabrication process based on a silicon carbide structural layer is presented. A partially conductive sintered target enables low-temperature dc sputtering of amorphous silicon carbide (SiC) at high deposition rates (75 nm/min). The low stress of the structural film allows for mechanically reliable structures to be fabricated, while the low-temperature deposition allows for pre-SiC metallization. The process is designed for low-cost film deposition and for complementary metal-oxide-semiconductor postintegration, stemming from chemical and thermal compatibility. Process flow, deposition, etching, and stress control are discussed, and a detailed process characterization is reported.

Published in:

Journal of Microelectromechanical Systems  (Volume:20 ,  Issue: 3 )