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Modeling on-chip variations in digital circuits using statistical timing analysis

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3 Author(s)
Petrosyan, G. ; Synopsys Armenia CJSC, Yerevan, Armenia ; Abovyan, S. ; Harutyunyan, T.

The purpose of this paper is to model timing of digital circuits by determining dependencies between the logical depth of standard cells in digital circuit and variation margins applied during timing analysis. The simulation results for the cells used in clock tree are presented.

Published in:

Design & Test Symposium (EWDTS), 2010 East-West

Date of Conference:

17-20 Sept. 2010