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Low-Power Off-Chip Memory Design for Video Decoder Using Embedded Bus-Invert Coding

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4 Author(s)
Ni Zhou ; Dept. of Electron. Eng., Tsinghua Univ., Beijing, China ; Fei Qiao ; Huazhong Yang ; Hui Wang

In this paper, a simple, efficient, low power off-chip memory design is proposed, which fully exploits the features of DRAM memory and video application, as well as overcomes the drawbacks of algorithm complexity and system modification of embedded compression, which is a popular way to decrease power consumption of the off-chip memory. The integration of the scheme into video decoder will not involve any extra video decoding complexity. It adopts the simple bus-invert encoding scheme. Based on the fact that the power consumption of logic `0' bit is less than that of logic `1', bus-invert encoding scheme is applied to the transferring data between video decoder and off-chip memory. Meanwhile, the features of fault tolerance of human eyes and lossy processing of video decoding application are exploited to solve the extra flag-bit of encoder scheme in off-chip SDARM memory, which has the fixed bit width and is less flexible than on-chip SRAM. This scheme is integrated into MPEG-2 decoder system. The experiment results show that this scheme can archive 20%-35% reduction in power consumption of logic `1' bit, and the objective quality of image has about 1.5db PSNR improvement on average.

Published in:

Autonomous Decentralized Systems (ISADS), 2011 10th International Symposium on

Date of Conference:

23-27 March 2011