Cart (Loading....) | Create Account
Close category search window
 

A 130- \mu W, 64-Channel Neural Spike-Sorting DSP Chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Karkare, V. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Gibson, S. ; Markovic, D.

Spike sorting is an important processing step in various neuroscientific and clinical studies. Energy-efficient spike-sorting ASICs are necessary to allow real-time processing of multi-channel, wireless neural recordings. Spike-sorting ASICs have to meet stringent power-density constraints and must provide significant data-rate reduction for wireless transmission. Most existing designs either provide only spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. In this paper, we demonstrate the design of a spike-sorting DSP chip that can perform detection, alignment, and feature extraction simultaneously for 64 channels. Spike-sorting algorithms chosen based on a complexity-performance analysis were implemented on ASIC using a MATLAB/Simulink-based architecture design framework. Energy-delay tradeoffs of the design were analyzed to identify the optimal degree of interleaving. The chip was implemented with a modular architecture, and can be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated when the chip is operated to process a reduced number of channels. The chip, implemented in a 90-nm CMOS process, has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels and provides a data-rate reduction of 91.25% (11.71 Mb/s to 1.02 Mb/s).

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 5 )

Date of Publication:

May 2011

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.