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In this paper, we present a new hardware-oriented, modified diamond search (HMDS) algorithm, for fast integer pel, motion estimation in H.264/AVC. We also present our co-designed, low power very large scale integration (VLSI) architecture for HMDS. The goal of HMDS is to enable the support of high quality video on low power mobile devices and low bit rate applications which typically use H.264/AVC baseline profile at levels 1-2. Our experiments use standard test sequences ranging from QCIF to high-definition 1280 × 720p video. The proposed VLSI architecture is prototyped as an field-programable gate array (FPGA)-based field programable system-on-chip. Our results show that HMDS on average has better rate-distortion performance and speedup, compared to previous state-of-the-art fast motion estimation algorithms, while its losses compared to full search motion estimation, are insignificant. Our prototyped architecture is more hardware-efficient than previous FPGA-based architectures in terms of power consumption, area, throughput, and memory utilization. We also show that its performance in terms of maximum frequency, minimum frequency, transistor count, and power consumption are comparable to that of state-of-the-art architectures implemented on application-specific integrated circuits.