Design of low power parallel pipeline ADC in 180nm standard CMOS process

This work describes a 9bit 200MSPS 0.18μm CMOS process four-stage parallel pipeline ADC with 2.5 bit per stage. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecture was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch generated charge injection error in order to maintain good overall accuracy. The designed ADC in this paper employs parallel architecture based on double sampling sample hold topology (DSSH) and shares the OTA between the same stages of two channels of the ADC. The ADC achieves 55.5dB SNDR and 41.3dB SFDR with 29.5mW power consumption from 1.8 V supply. The resulting FOM is 0.304 PJ/conversion step. The high speed specification of the system requires the design of low offset comparator.