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Accelerating Parameter Sweep Applications Using CUDA

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3 Author(s)
Motokubota, M. ; Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan ; Ino, F. ; Hagihara, K.

This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications with irregular access patterns, which usually result in lower performance on the GPU. The key idea to resolve this irregularity is to exploit the similarity of data accesses between different parameters. That is, the scheme simultaneously processes multiple parameters instead of a single parameter. This simultaneous sweep allows data accesses to be coalesced into a single access if the irregularity appears similarly at every parameter. It also reduces the amount of off-chip memory access by using fast on-chip memory for the data commonly accessed for multiple parameters. As a result, the scheme achieves up to 4.5 times higher performance than a naive scheme that processes a single parameter by a kernel invocation.

Published in:

Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on

Date of Conference:

9-11 Feb. 2011