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The high performance of elliptic curve (EC) crypto system depends essentially an efficient arithmetic in the underlying finite field. Many hardware designs of elliptic curves cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field Programmable Gate Arrays (FPGA). The proposed architecture based on Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for GF(2163) field arithmetic. To achieve high throughput rates, we designed two new word-level arithmetic units over GF(2163) and derived parallelized elliptic curve point doubling and addition algorithms with uniform addressing based on Lopez-Dahab method. We implemented our design using Xilinx XC4VLX200 FPGA device which uses 16,209 slices and has a maximum frequency of 143 MHZ. This design roughly 4.8 times faster with two times increased hardware complexity compared with the previous proposed ones and GF (2193) research was based on using the efficient Montgomery add and double algorithm, the Karatsuba-Offman multiplier and the Itoh-Tsjuii algorithm for the inverse component. The hardware design was based upon an optimized Finite State Machine (FSM), with a single cycle 193 bits multiplier, field adder and a field squarer. The different optimizations at the hardware level improve the acceleration of the ECC scalar multiplication; increases frequency and speed of operation such as key generation, encryption and decryption.