Modified SET D-Flip Flop Design for Low-Power VLSI Applications

Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the portable applications. Design is tested for various substrate bias voltages in sub-threshold region to opt for better design. Design comparison between previously reported design and modified design is performed at 65nm and 45nm to show technology independence. Comparative simulation results show that area and power efficient SET D-FF design is better choice for portable applications.