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A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration

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2 Author(s)
Daigneault, M. ; Dept. of Electr. Eng., Ecole Polytech. de Montreal, Montreal, QC, Canada ; David, J.P.

A high-resolution high-precision time-to-digital converter (TDC) architecture is presented for implementation on field-programmable gate arrays (FPGAs) supporting dynamic reconfiguration. The proposed architecture relies on multiple parallel high-resolution delay lines implemented by the programmable interconnection points within the routing switch fabric. These delay lines feature a 1-ps resolution over a range of 3 ns. A calibration process is proposed to take process-voltage-temperature variations, as well as clock skew, into account. A TDC with a 50-ps resolution and precision as high as 35 ps has been implemented on a Virtex-II Pro FPGA. Results show that the proposed architecture and calibration process can be used to achieve resolutions as fine as 10 ps.

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:60 ,  Issue: 6 )

Date of Publication:

June 2011

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