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A physics-based compact model is developed for III-V field-effect transistors for digital logic applications. Quasi-ballistic ratios, trapezoidal quantum-well subband energy levels, and 2-D source/drain influence on both electrostatics and capacitance are considered. Furthermore, gate tunneling leakage current and parasitic capacitance models are included. These latter effects are important in future technology logic applications, particularly in circuits such as high-density cache arrays. In this paper, we describe the III-V compact model including the gate leakage current and parasitic capacitance analytical models. The efficacy of the compact model in a practical circuit environment is demonstrated using transient simulations of a 6T-static random access memory cell. In addition, we provide design guidelines for optimization of the intrinsic and the extrinsic structure with regard to the parasitic effects.