By Topic

Automatic Hardware Reconfiguration for Current Reduction at Low Power in RFIC PAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Constantin, N.G. ; Dept. of Electr. Eng., Ecole de Technol. Super., Montreal, QC, Canada ; Zampardi, P.J. ; El-Gamal, M.N.

This paper presents a novel hardware reconfiguration technique implemented in a dual integrated-circuit (IC) GaAs HBT power amplifier (PA) design and demonstrates reduced current and improved efficiency at low power. The method automatically reconfigures the hardware of an RF IC PA over a given power transmission. Hardware interfacing and synchronization from outside the PA is minimized, and automatic gain compensation upon hardware reconfiguration is achieved with minimal temperature-dependant calibration. The challenge of integrating such complex on-chip hardware functions in a GaAs HBT technology was circumvented by the introduction of a gating concept used in conjunction with envelope feedback, and careful tradeoffs between circuit complexity and performance. Designs that suit the on-chip integration of the technique in GaAs HBT or Si bipolar junction transistor technologies are described. Experimental data are reported to support the proposed method.

Published in:

Microwave Theory and Techniques, IEEE Transactions on  (Volume:59 ,  Issue: 6 )