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CMOS scaling into the nanometer regime

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11 Author(s)
Yuan Taur ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Buchanan, D.A. ; Wei Chen ; Frank, D.J.
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Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling

Published in:

Proceedings of the IEEE  (Volume:85 ,  Issue: 4 )

Date of Publication:

Apr 1997

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