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The ZEUS central tracking detector first level trigger processor

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8 Author(s)
R. Hallsall ; Rutherford Appleton Lab., Chilton, Didcot, UK ; S. Jaroslawski ; S. Madani ; G. P. Heath
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The first-level trigger is a programmable 20-MHz pipelined machine based on user-programmable gate arrays, SRAMs (static random access memory) and other PLDs (programmable logic devices). The authors give an overview of the processor and concentrate on the design of the main track finding module, cell processor 1 (CP1). The design demonstrates the techniques required for a fast continuous pipelined multicrate trigger, where the processing time is greater than the drift time and the beam-crossing rate. A fundamental limitation occurs when events are closer together than the drift time, thus becoming merged. The higher beam-crossover rate of future machines would be accommodated by improvements in circuit speed and density

Published in:

IEEE Transactions on Nuclear Science  (Volume:37 ,  Issue: 3 )