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Differentially-tuned low-spur PLL using 65 nm CMOS process

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4 Author(s)
Yun, S.-J. ; ETRI (Electron. & Telecommun. Res. Inst.), Daejeon, South Korea ; Lee, H.D. ; Kim, K.-D. ; Kwon, J.-K.

A differentially-tuned LC-VCO PLL using a transformer-resonator and a loop-phase control scheme is proposed. The phase of a control path between the differential controls is adjusted to suppress spurious tones. The measured results for the proposed PLL, implemented in a CMOS 65 nm process, show operation frequencies of 3.5-5.6 GHz, phase noise of -118.5 dBc/Hz at 1 MHz offset, and spur rejection of 73 dB, while dissipating 3.2 mA at 1 V supply.

Published in:

Electronics Letters  (Volume:47 ,  Issue: 6 )

Date of Publication:

March 17 2011

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