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Through-silicon via (TSV) is an important enabler for future 3-D integration of integrated circuits. TSV typically contains a high-aspect-ratio metal via embedded in silicon and electrically isolated from the silicon by a layer of dielectric liner hence forming a metal-oxide-semiconductor structure. The parasitic capacitance introduced by TSV must be kept as low as possible for low latency signal transmission. It is also equally important to ensure that the capacitance within the operating voltage is stable. It is shown that careful process tuning can induce the appropriate oxide fixed charge (|Qf| ~ 8.4 × 1011 cm-2) in order to shift the CV curve such that the TSV capacitance is kept stable at the value of accumulation capacitance (Cox) within the operating voltage range of interest (~0-5 V).