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Minimal Instruction Set FPGA AES processor using Handel — C

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4 Author(s)
J. H. Kong ; University Of Nottingham Malaysia Campus, Jalan Broga, Semenyih, 43500 Selangor, Malaysia ; L. -M. Ang ; K. P. Seng ; Achonu Oluwole Adejo

This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless sensor networks and other low complexity systems which may have severely constrained physical memory requirements. With the availability of the FPGA technology, aids practical implementation of the data encryption purpose processor.

Published in:

Computer Applications and Industrial Electronics (ICCAIE), 2010 International Conference on

Date of Conference:

5-8 Dec. 2010