By Topic

Low-power fast static random access memory cell

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
C. M. R. Prabhu ; Faculty of Engineering and Technology, Multimedia University, Melaka, Malaysia ; Ajay Kumar Singh

In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line. The simulated result shows that the write power saving is at least 86.95% in 0.12μm technology compared to the conventional cell. The access delay is also found to be lower than the conventional SRAM cell during write operation. The static noise margin (SNM) is maintained after carefully sizing the tail transistors.

Published in:

Computer Applications and Industrial Electronics (ICCAIE), 2010 International Conference on

Date of Conference:

5-8 Dec. 2010