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In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line. The simulated result shows that the write power saving is at least 86.95% in 0.12μm technology compared to the conventional cell. The access delay is also found to be lower than the conventional SRAM cell during write operation. The static noise margin (SNM) is maintained after carefully sizing the tail transistors.