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A CMOS down-conversion mixer with high linearity and low noise figure in 0.18-μm technology

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3 Author(s)
Ziabakhsh, S. ; Roudsar & Amlash Branch, Dept. of Electr. Eng., Islamic Azad Univ., Roudsar, Iran ; Cheraghi, G. ; Alavi-Rad, H.

This paper presents a highly linear CMOS active balanced down-conversion mixer in a TSMC 0.18 μm process for 2.4 GHz application. The proposed mixer uses the current bleeding technique and an extra LC filter to improve the noise figure (NF) and linearity. Also, with an extra LC filter in switching stage and the careful choosing of transistor sizes, the mixer has a better performance in term of IIP3, IIP2, NF, and isolation. The simulation results show the IIP3 of 8 dBm, the DSB NF of a 9.2 dB, and higher than 60 dBm of IIP2. The total DC power consumption of this mixer is 10.8 mW from a 1.8 V supply voltage. The excellent LO-RF and LO-IF isolation achieved of 170 dB and RF-IF achieved of 86.76 dB.

Published in:

Circuits and Systems for Communications (ECCSC), 2010 5th European Conference on

Date of Conference:

23-25 Nov. 2010