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In this paper, we propose a design methodology for a low-power CMOS LNA consisting of a common-gate stage with modified input matching circuitry and inductive inter-stage architecture for 2450-MHz Band IEEE 802.15.4/ZigBee standard. This configuration provides better input matching, lower noise figure and further reverse isolation which is vital in LNA design. Simulation results show a gain of 16.85 dB, a noise figure of 1.24 dB, an IIP3 of 12.6 dBm and -21.22 dB input matching (S11) for the LNA. The circuit operates at the supply voltage of 1.8 V and power dissipation of 4 mW.