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Multicore Simulation of Transaction-Level Models Using the SoC Environment

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3 Author(s)
Weiwei Chen ; Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, CA, USA ; Xu Han ; Doemer, R.

Editor's note: To address the limitations of discrete-event simulation engines, this article presents an extension of the SoC simulation kernel to support parallel simulation on multicore hosts. The proposed optimized simulator enables fast validation of large multicore SoC designs by issuing multiple simulation threads simultaneously while ensuring safe synchronization.

Published in:

Design & Test of Computers, IEEE  (Volume:28 ,  Issue: 3 )