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Decreasing the power consumption of CMOS digital circuits by both supply voltage (V/sub B/) and threshold voltage (V/sub T/) reduction (by technology) is limited by the V/sub T/ spread (technology and temperature dependent). This paper presents a control circuit that minimizes the sum of the dynamic and static power consumption by reducing and controlling both the supply and threshold voltages. To compensate for temperature and technology variations, the latter is electrically adjusted by bulk biasing. The control loop has been designed such that the speed is maintained.