Referenced Items are not available for this document.
The paper proposes a method to realize low-power control-logic modules by combining transistor-size optimization and transistor layout. When applied to a circuit with 10,000 transistors, the optimizer has reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.
Published in:
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Date of Conference: 10-12 Oct. 1994
- Page(s):
- 50 - 51
- Meeting Date :
- 10 Oct 1994-12 Oct 1994
- Print ISBN:
- 0-7803-1953-2
- INSPEC Accession Number:
- 5093367
- Conference Location :
- San Diego, CA, USA
- Digital Object Identifier :
- 10.1109/LPE.1994.573199
- Product Type:
- Conference Publications
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