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A high-level synthesis methodology for low-power VLSI design

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3 Author(s)
Goodby, L. ; Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA ; Orailoglu, A. ; Chau, P.M.

A high-level synthesis methodology for low-power design is described. With the objective of supporting the design of low-power, performance-constrained systems such as signal processing applications, the methodology enables the designer to place throughput and latency constraints on the synthesized design. A library-based design style is used, where libraries may include multiple implementations of each component type. Library components are characterized by their relative power, area, and delay performance. The methodology has been implemented in the Sierra high-level synthesis system.

Published in:

Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium

Date of Conference:

10-12 Oct. 1994

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