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An 8-bit, 150 MS/s folding and interpolating ADC in 0.25 μm CMOS with resistive averaging

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3 Author(s)

An 8-bit, 150 MS/s folding interpolating ADC in a digital CMOS technology is described. The developed converter uses resistor interpolation method along with the fully-differential, continuous-time, and open-loop circuitry in order to achieve a high speed operation with low area and power consumption. Also the number of latches in the digital encoder block is reduced using previously described analog encoding. The simulation results of the converter in 0.25 μm CMOS are presented. The ADC power dissipation from a 3V power supply is 310 mW at 150 MHz sampling rate.

Published in:

Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on  (Volume:2 )

Date of Conference:

0-0 2003