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In this paper, we deal with reducing the effect of non-ideality affecting memory cells build in switched current (SI) technique. The basic idea consists of combining benefits of two improved techniques. Indeed, we demonstrate that class AB cells built in the grounded gate configuration and used with S2I technique improve the performance of SI cells. As a consequence errors hitting output current are minimized and dynamic range is maximized. The proposed cell is designed using CMOS 0.35 μm process. With 3.3V power supply voltage, this new memory cell achieves a 80 dB dynamic range at 16 MHz sampling frequency, where the power consumption is about 860 μW. These performances are reached using a new methodology to optimize transistor sizes.
Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on (Volume:2 )
Date of Conference: 0-0 2003