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With technology improvements, the main bottleneck in single chip systems in terms of performance, power consumption, and design reuse is proving to be generated by the on-chip communication architecture. Therefore, packet oriented on-chip interconnection schemes have been proposed as an alternative to traditional bus-based structures, which are inherently non scalable. However, such interconnection architectures have to be during the very early stages of the design flow. The objective of this work is to present an application independent stochastic framework for high level performance analysis of networks-on-chip based communication architectures. Such a template allows the designer the performance evaluation of various competing on-chip communication architectures early in the design flow.