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Design methodology for the IBM POWER7 microprocessor

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25 Author(s)
Friedrich, J. ; IBM Systems and Technology Group, Austin, TX, USA ; Puri, R. ; Brandt, U. ; Buehler, M.
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The IBM POWER7® microprocessor, which is the next-generation IBM POWER® processor, leverages IBM's 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex 567-$hbox{mm}^{2}$ die, the IBM design team made significant innovations in chip design methodology. This paper describes the most critical methodology innovations specific to POWER7 design, which were in modularity, timing closure, and design efficiency.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

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IBM Journal of Research and Development  (Volume:55 ,  Issue: 3 )