By Topic

Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Jang-Gn Yun ; Semicond. R&D Center, Samsung Electron. Co. Ltd., Suwon, South Korea ; Kim, G. ; Joung-Eob Lee ; Yoon Kim
more authors

In this paper, a 3-D NAND Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on NAND Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line NAND Flash memory application.

Published in:

Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 4 )