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Environment Modelling for Tighter Timing Analysis of Synchronous Programs

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3 Author(s)
Andalam, S. ; Dept. of Electr. & Comput. Eng., Univ. of Auckland, Auckland, New Zealand ; Sinha, R. ; Roop, P.S.

Static timing analysis of a hard real-time application is necessary to ensure that task-level timing deadlines are always met. In many cases, it is preferable to include details about the operating environment to ensure precise timing analysis. However, adding an environment model increases the overall state space being analyzed, which can result in longer analysis time. In this paper, we present three approaches for modelling the environment. The first approach, which uses variables, provides precise timing results but causes state space explosion. This tremendously increases analysis time. The second approach, which uses real-valued clocks, provides an abstraction over variables that helps reduce the analysis time, when we trade-off precision. A third approach, based on a heuristic, uses a combination of both variables and clocks, and can optimize the state space while achieving precise timing results. Experimental results show that the proposed heuristic achieves a 91% reduction in the state-space as compared to using variables, while maintaining the same precision.

Published in:
Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on

Date of Conference: 17-19 Jan. 2011

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