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A novel all-digital 50% duty cycle corrector (DCC) is pro- posed in this paper. The DCC features include a delay unit based on precharge logic gates with low delay time and a robust SR latch under process voltage and temperature variations for final edge combination over wide frequency and duty-cycle ranges. The rising edge of the output clock has a constant delay when comparing to the input clock, which makes it easy to cooperate with a delay locked loop. The circuit is fabricated in Chartered 0.18-μm CMOS process. The acceptable input clock frequency ranges from 400 MHz to 2 GHz. The correcting error is ±3.5% at 1 GHz or ±1% at 400 MHz.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:20 , Issue: 4 )
Date of Publication: April 2012