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Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores

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4 Author(s)
Shyue-Kung Lu ; Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan ; Shi-Yu Huang ; Cheng-Wen Wu ; Yin-Mou Chen

This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

Published in:

Design & Test of Computers, IEEE  (Volume:28 ,  Issue: 4 )

Date of Publication:

July-Aug. 2011

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