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A 60 GHz high gain transformer-coupled differential power amplifier in 65nm CMOS

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6 Author(s)
Jenny Yi-Chun Liu ; Department of Electrical Engineering, University of California, Los Angeles, 90095, USA ; Qun Jane Gu ; Tim LaRocca ; Ning-Yi Wang
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A fully differential 60 GHz three-stage transformer-coupled amplifier is designed and implemented in 65 nm digital CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanisms, and simultaneous input/inter-stage/output matching networks are used to facilitate a compact circuit design. With a cascoded circuit configuration, the amplifier is tested with a linear gain of 30.5 dB centered at 63.5 GHz and a -40 dB reverse isolation under a 1 V supply. The amplifier delivers 9 dBm and 13 dBm output power under 1 V and 1.5 V supplies, respectively and occupies a core chip area of 0.05 mm2. The measurement results validate a high gain and area efficient power amplifier design methodology in deep-scaled CMOS for millimeter-wave communication system applications.

Published in:

2010 Asia-Pacific Microwave Conference

Date of Conference:

7-10 Dec. 2010