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A 2.5-2.7 GHz pseudo-cascode CMOS receiver front-end with integrated unequal-turn-ratio transformer balun

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4 Author(s)
Lin, Y.-C. ; Dept. of Electr. Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan ; Chen, K.-S. ; Horng, T.-S. ; Wu, J.-M.

In this paper, a 2.5-2.7 GHz direct conversion receiver front-end including a low-noise amplifier (LNA) based on a resistive shunt-feedback inverter configuration, an on-chip transformer balun of unequal turn ratio for impedance matching, and a current-driven passive mixer is presented. The LNA uses a two-stage amplifier topology established from inverters and resistors to improve the third-order intermodulation distortion (IMD3). To lower the supply voltage, the LNA output connects to an on-chip transformer balun to convert the single-ended signal into a differential one for feeding to the mixer. The proposed receiver front-end is implemented in 0.18-μm CMOS foundry process. It achieves a conversion gain between 19.3 to 20.1 dB, a noise figure between 3.79 to 3.84 dB, and an input 1-dB compression point (IP1dB) between -11.1 to -14.5 dBm. The maximum (IMD3) product of the proposed receiver front-end is -32 dBc at the input RF power of -18 dBm, and the input third-order intercept point (IIP3) is between -3 to -5.5 dBm at the dc power consumption of 15 mW from a 1.2-V power supply.

Published in:

Microwave Conference Proceedings (APMC), 2010 Asia-Pacific

Date of Conference:

7-10 Dec. 2010