Skip to Main Content
In this study, speed-up of a three-dimensional finite difference time domain (FDTD) method is examined using the Cell broadband engine (Cell/B.E.) processor. In the past, direct memory access (DMA) calculation time was a problem in view of the speed-up of the FDTD method when the calculation domain was large e.g., a 3D calculation domain. To prevent this problem, continuous memory access between the main memory and local store (LS) of synergistic processor elements (SPEs) by DMA is examined. Further, software pipelining is implemented in a SPE program by considering processing dependence in FDTD method. As a result, a linear speed-up rate is obtained when several SPEs are used. Moreover, when 8 SPEs are used and a vectorzed SPE code is employed, the speed-up rate is approximately 24 times. The proposed programming techniques are validated form the obtained results.