By Topic

Acceleration of finite difference time domain method using cell broadband engine processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shinya Watanabe ; Department of Electrical Engineering and Electronics, College of Science and Engineering, Aoyama Gakuin University, 5-10-1 Fuchinobe, Sagamihara-shi, Kanagawa, 229-8558 Japan ; Osamu Hashimoto

In this study, speed-up of a three-dimensional finite difference time domain (FDTD) method is examined using the Cell broadband engine (Cell/B.E.) processor. In the past, direct memory access (DMA) calculation time was a problem in view of the speed-up of the FDTD method when the calculation domain was large e.g., a 3D calculation domain. To prevent this problem, continuous memory access between the main memory and local store (LS) of synergistic processor elements (SPEs) by DMA is examined. Further, software pipelining is implemented in a SPE program by considering processing dependence in FDTD method. As a result, a linear speed-up rate is obtained when several SPEs are used. Moreover, when 8 SPEs are used and a vectorzed SPE code is employed, the speed-up rate is approximately 24 times. The proposed programming techniques are validated form the obtained results.

Published in:

2010 Asia-Pacific Microwave Conference

Date of Conference:

7-10 Dec. 2010