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A 57–66 GHz medium power amplifier in 65-nm CMOS technology

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4 Author(s)
Chia-Yu Hsieh ; Department of Electrical Engineering and Graduated Institute of Communication Engineering, National Taiwan University, No. 1, Sec. 4, Roosevlt Road, Taipei, 10617 Taiwan ; Jhe-Jia Kuo ; Zuo-Min Tsai ; Kun-You Lin

This paper presents the design and measurement results of a 57-66 GHz medium power amplifier in 65-nm LP CMOS process. This amplifier is designed with broadband matching concern, which can achieve a measured gain more than 21 dB from 57-66 GHz and have a 3-dB bandwidth more than 14 GHz while consuming 54 mW from a 1.2 V supply. The measured results exhibit Psat of 10.3 dBm, P1dB of 6.2 dBm, and the peak PAE is 16 %at 58 GHz. The chip size is only 0.3 mm2.

Published in:

2010 Asia-Pacific Microwave Conference

Date of Conference:

7-10 Dec. 2010