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State model for scheduling Built-in Self-Test and scrubbing in FPGA to maximize the system availability in space applications

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3 Author(s)
Agarwal, A. ; Comput. Eng. Dept., Netaji Subhas Inst. of Technol., New Delhi, India ; Bhatia, G. ; Chakraverty, S.

Reconfigurable Field Programmable Gate Arrays (rFPGAs) are employed extensively in spacecraft electronic systems to implement low-power adaptable systems that provide high density functionality. A challenge that must be tackled during system design is their high susceptibility to radiation induced Single Event Upsets (SEUs). A burst of energized particles may cause extensive damage to circuits. Even if their presence is transient, SEU faults may cause a permanent failure when they afflict the configuration memory - SRAM. There are two ways in which timely detection of faults and timely action to circumvent them can be undertaken - (i) Online error detecting/correcting circuits that demand a high premium in terms of FPGA area for extending error-security and Fault Tolerance, thus increasing cost and redundancy, and (ii) Built-in Self-Test (BIST) that allows efficient and very high-coverage fault detection but the fault testing is performed off-line. In general, Reliability and Availability (R&A) is a crucial quality parameter. In this paper, we present a state model that schedules Self-tests judiciously to optimize availability while ensuring a high degree of reliability. The aim of system design is to determine an optimal value of the mean time to self testing λT so that faults are detected on time and are reconfigured to boost system availability.

Published in:

Power Electronics (IICPE), 2010 India International Conference on

Date of Conference:

28-30 Jan. 2011