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A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

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7 Author(s)
Dajiang Zhou ; Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan ; Jinjia Zhou ; Xun He ; Jiayi Zhu
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The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096×2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 4 )