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A multi-step word-line control technology (MWC), combined with a new hierarchical cell SRAM architecture (HCA), has been developed to overcome rapid increase in random variability with no area penalty. A 40-nm-node 0.248-μm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit density to 2.98 Mb/mm2. MWC improved VDD_min@-6σ by 0.34 V and 0.22 V for read and write operations, respectively, enabling stable 1.0 V operations. Four nanosecond SRAM access time is achieved by adopting HCA, which cancels out a 1.4 ns increase of access delay caused by MWC.