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General purpose parallel processing machines are increasingly being used to speedup a variety of VLSI CA D applications. This paper addresses the mapping of logic simulation using the time first algorithm on parallel machines by exploting the concurrency available in the circuit being simulated. The speedup obtained on parallel/distributed simulation, depends on two major factors, the amount of simulation concurrency possible, and the amount of messages that must be passed among processors. Logic simulation using Time. First algorithm has been mapped to a distributed platform using a network of workstations. In this paper we propose a partitioning algorithm, which drastically reduces the interprocessor communication and also gives better simulation time. Reduction of communication data up to 4t0% with eight processors have been obtained for ISCAS benchmark circuits. Reduction of simulation time was also observed.