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A 10 ns 54×54-bit parallel structured full array multiplier with 0.5 μm CMOS technology

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9 Author(s)

A 54-b×54-b multiplier fabricated in double metal 0.5-μm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-b×54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mm×3.45 mm

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990