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A 1 V operating 256-Kbit full CMOS SRAM

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6 Author(s)

A full CMOS six-transistor memory cell was fabricated with single-polysilicon, double-metal technology. The channel lengths of n-channel and p-channel transistors are 0.8 μm and 1.2 μm and the cell sizes are 8.5 μm×12.8 μm, respectively. The gate oxide thickness is 200 Å, and the lightly doped drain (LDD) structure is adopted for the n-channel transistor. A 256-kb full CMOS SRAM utilizing the new technology has achieved a wide operating voltage from 1 V to 7 V and 5 mW (at f=1 MHz & VCC=5 V) and 0.2 mW (at f=1 MHz & VCC=1 V) power dissipation. The address input and data output signals with 100 pF load capacitance of V CC=1 V are shown

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990