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An experimental 5 ns BiCMOS SRAM with a high-speed architecture

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15 Author(s)

A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory cell of 28 μm2

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990