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An experimental 2T cell RAM with 7 ns access time at low temperature

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2 Author(s)

A novel two-transistor DRAM cell technology is introduced which uses a unique clamped bit line, unbalanced-gain sense amplifier. The 2T cell topology offers nondestructive readout of the cell state and high-speed operation. The speed of the sense amplifier is independent of bit-line capacitance, and the bit lines of the new topology are insensitive to noise voltage coupling. The memory exhibits access times of 12.4 ns at 298 K and 7 ns at 89 K. The design is well suited to quasi-static low-temperature memory operation and high-speed cache memory applications

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990