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A CCD based neural network integrated circuit with 64K analog programmable synapses

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3 Author(s)

A report is presented on the design, fabrication, and testing of a neural network integrated circuit with 65536 analog programmable synapses (256 fully interconnected neurons). The integrated circuit utilizes charge-coupled devices (CCDs) based on a generic architecture that the authors proposed (1987). Preliminary testing of the CCD neural processor indicates that the operating speed is 0.5×109 analog interconnect updates/s. Loading of the synaptic interaction matrix can be accomplished either electrically or optically within 0.5 ms or 1 ms, respectively

Published in:

Neural Networks, 1990., 1990 IJCNN International Joint Conference on

Date of Conference:

17-21 June 1990

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