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Implementation of digital HDTV video decoder by multiple multimedia video processors

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7 Author(s)

A digital HDTV video decoder system is designed and implemented by using multiple multimedia video processors in a loosely coupled architecture. This decoder decompresses video bitstream up to 20 Mbits/s and produce analog output at HDTV pixel rate. This design has the advantages of low cost and small system size.

Published in:

Consumer Electronics, 1996. Digest of Technical Papers., International Conference on

Date of Conference:

5-7 June 1996