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An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

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8 Author(s)
Yamaguchi, K. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Nanbu, H. ; Kanetani, K. ; Homma, N.
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An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune switched-load-resistor memory cell with clamp transistors, an upward-transistor decoder utilizing a SIdewall-base COntact Structure (SICOS) upward transistor for the AND gate, a Darlington word driver with advanced discharge circuits, and 0.8- mu m SICOS technology. High-load and low-load resistors in this new memory cell are formed by using double-layer polysilicon for the base and emitter electrodes in the SICOS structure. This results in a small cell size (498 mu m2) and a reasonable chip size (85.8 mm2). An accelerated soft-error test using americium alpha source shows that the new 64-kbit RAM has sufficient soft-error immunity, in spite of its small cell capacitance which is about one third that of conventional RAM's. In addition to the new memory cell, the upward-transistor decoder and the Darlington word driver with advanced discharge circuits make it possible to realize a high-speed, large-capacity bipolar RAM, while maintaining soft-error immunity.

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Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 5 )