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A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

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9 Author(s)
Benschneider, B.J. ; Digital Equipment Corp., Hudson, MA, USA ; Bowhill, W.J. ; Copper, E.M. ; Gavrielov, M.N.
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A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.

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Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 5 )