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The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm2 chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.